1. Field of the Invention
The present invention is related to a D/A converter for outputting an analog signal in correspondence with a digital input signal.
2. Description of the Related Art
Very recently, since fine processing techniques of semiconductor integrated circuits are specifically improved, there is great progress in digital processing techniques for conventional analog processing systems. In digital processing systems, there are many possibilities that input/output signals of such digital processing systems are produced in analog signal forms. Therefore, digital-to-analog (D/A) converters capable of converting digital signals into analog signals are necessarily required in such digital processing systems, the important aspect of which is considerably increased.
Subsequently, a conventional D/A converter will now be explained. FIG. 10 shows a structural diagram of an n-bit D/A converter. Reference numeral 10 indicates an n-bit digital input signal, and reference numeral 11 represents a decode circuit for outputting xe2x80x9ckxe2x80x9d pieces of control signals used to select a predetermined current cell circuit in response to the digital input signal 10. Symbol xe2x80x9ckxe2x80x9d is equal to xe2x80x9c2nxe2x88x921.xe2x80x9d Also, reference numeral 12 indicates xe2x80x9ckxe2x80x9d pieces of current cell selection signals which are outputted from the decode circuit 11, and reference numeral 13 represents xe2x80x9ckxe2x80x9d pieces of current cell circuits which are 25 selected by the current cell selection signal 12 and also own values equal to each other. Reference numeral 14 denotes an output current which is produced by adding such output currents of current cell circuits selected by the current cell selection signal 12 among all of the current cell circuits 13, reference numeral 15 indicates another output current which is produced by adding such output currents of current cell circuits other than the current cell circuits selected by the current cell selection signal 12 among all of the current cell circuits 13. Also, reference numeral 16 shows a current-to-voltage converting circuit for converting the output current 14 into a voltage corresponding thereto, reference numeral 17 denotes a current-to-voltage converting circuit for converting the output current 15 into a voltage corresponding thereto, reference numeral 18 represents an analog output terminal from which the voltage converted by the current-to-voltage converting circuit 16 is outputted, and reference numeral 19 shows an analog output terminal from which the voltage converted by the current-to-voltage converting circuit 17 is outputted.
FIG. 11 is a structural diagram for showing a structure of the current cell circuit 13. Reference numeral 20 shows a current cell selection signal, reference numeral 21 represents a constant current source for supplying a unit current xe2x80x9cixe2x80x9d, reference numeral 22 indicates a current output terminal to which the current xe2x80x9cixe2x80x9d is supplied in the case that the current output terminal is selected by the current cell selection signal 20, and reference numeral 23 indicates a current output terminal to which the current xe2x80x9cixe2x80x9d is supplied in such a case that the current output terminal is not selected by the current cell selection signal 20. Also, reference numeral 24 shows a Pch transistor having a switch function and connected to a current path provided on the side of the current output terminal 22, reference numeral 25 represents another Pch transistor having a switch function and connected to a current path provided on the side of the current output terminal 23, and also reference numeral 26 shows an inverter for inverting the current cell selection signal 20 which is supplied to the gate of the Pch transistor 24.
Next, a description will be made of operations of the current cell circuit of FIG. 11. As indicated in FIG. 11, the current cell selection signal 20 is supplied to the gate of the Pch transistor 25, and also is supplied via the inverter 26 to the gate of the Pch transistor 24 so as to activate the switch function of any one of the current paths of the current cell circuits, so that the output currents derived from the current output terminals 22 and 23 are controlled.
FIG. 12 shows a relationship explanatory diagram for explaining the current cell selection signal 20 (SEL), and values of currents supplied to both the current output terminal 22 and the current output terminal 23. In such a case that the current cell selection signal 20 (SEL)=1, since the Pch transistor 24 (TP1) is turned ON and the Pch transistor 25 (TP2) is turned OFF, the unit current xe2x80x9cixe2x80x9d is supplied only to the current output terminal 22 whereas the unit current xe2x80x9cixe2x80x9d is not supplied to the current output terminal 23. Contrary to the above case, in such a case that the current cell selection signal 20 (SEL)=0, since the Pch transistor 25 (TP2) is turned ON and the Pch transistor 24 (TP1) is turned OFF, the unit current xe2x80x9cixe2x80x9d is supplied only to the current output terminal 23 whereas the unit current xe2x80x9cixe2x80x9d is not supplied to the current output terminal 22.
FIG. 13 is a structural diagram of the current-to-voltage converting circuits 16 and 17. Reference numeral 40 indicates a current input terminal, reference numeral 41 shows an input current having a current value xe2x80x9cIxe2x80x9d, reference numeral 42 indicates a resistive element having a resistance value xe2x80x9cRxe2x80x9d, and reference numeral 43 indicates a voltage output terminal. Next, a description will be made of operations of the current-to-voltage converting circuits 16 and 17. The input current 41 entered from the current input terminal 40 flows entirely via the resistive element 42 to the ground at the zero potential. At this time, such a voltage defined by Ixc3x97R is produced at the voltage output terminal 43 based upon the law of Ohm.
Now, operations of the n-bit D/A converter with employment of the above-explained circuit arrangement shown in FIG. 10 will be described. Assuming now that a total number of the above-explained current cell circuits 13 is xe2x80x9cmxe2x80x9d (symbol xe2x80x9cmxe2x80x9d=0, 1, 2, . . . , k) which are selected in response to the digital input signal 10, the output current 14 becomes xe2x80x9cmxc3x97i,xe2x80x9d and the output current 15 becomes (kxe2x88x92m) X i. As a consequence, in the case that both the current-to-voltage converting circuit 16 and the current-to-voltage converting circuit 17 are arranged by the resistive element having the resistance value xe2x80x9cRxe2x80x9d, such a voltage having a value of xe2x80x9cmxc3x97ixc3x97Rxe2x80x9d is outputted from the analog output terminal 18, and such a voltage having a value of xe2x80x9c(kxe2x88x92m)xc3x97ixc3x97Rxe2x80x9d is outputted from the analog output terminal 19. In this case, since symbol xe2x80x9cmxe2x80x9d may own values from xe2x80x9c0xe2x80x9d to (2nxe2x88x921), it is possible to realize such a D/A converter having (2n) pieces of gradation, namely n-bit resolution in response to the digital input signal.
However, the above-explained conventional D/A converter owns the below-mentioned problems. That is, in the conventional D/A converter having the above-described structure, the unit current is realized by the constant current source. As a result, a plurality of constant current sources are required whose total number is equal to the necessary gradation number. For instance, in the case of a 10-bit D/A converter, 1023 (=210) pieces of such constant current sources are necessarily required. Since the respective constant current sources are made of analog elements, the occupied area of these constant current sources which occupy the silicone wafer within the semiconductor integrated circuit is large. Moreover, in such a case that the resolution is increased by 1 bit, the resultant occupied area becomes approximately two times. Since product cost of a semiconductor integrated circuit largely depends upon an occupied area of this circuit, such a circuit design must be avoided which may induce an increase of the occupied area. In such a technical field of digital mobile communication terminal apparatuses which are known as typical digital processing systems, area-reducing of semiconductor integrated circuits which constitute major circuit components are very important, while terminal apparatuses are gradually made compact and in light weight. Furthermore, when the occupied area on the silicon wafer of the semiconductor integrated circuit is increased, the fluctuations of the respective circuit components on the circuit plane are increased. Otherwise, the wiring line length is made longer. As a result, the adverse influences caused by the impedances of the respective wiring lines are increased, which could deteriorate the precision of the D/A converter.
The present invention has been made to solve the above-explained structural problems, and therefore, has an object to provide such a D/A converter capable of reducing an occupied area of a circuit and at the same time capable of improving resolution by largely reducing a total number of circuit components thereof, as compared with the structure of the conventional D/A converter.
A D/A converter, according to a first aspect of the present invention, is featured by such a D/A converter comprising: a constant current source (constant current source 503); a switch group constituted by switch circuits (switch circuit 504), which is series-connected to the constant current source, and is operated in response to a control signal (current path selection signal 502) to form a plurality of current paths for equally dividing a constant current of the constant current source; decode means (decode circuit 501) for outputting the control signal used to control operations of the switch circuits in response to a digital input signal (digital input signal 500); and current-to-voltage converting means (current/voltage converting circuit 508) for adding currents to each other which are outputted via the current paths of the switch circuits so as to convert the added currents into a voltage.
A D/A converter, according to a second aspect of the present invention, is featured by that in the D/A converter, the constant current is obtained by employing a resistive element (resistive element 511) having one end to which a constant voltage is added instead of the constant current source.
A D/A converter, according to a third aspect of the present invention, is featured by that in the D/A converter, the constant current source is a single constant current source; the switch circuit includes: a plurality of lower-stage switching elements (Pch transistors 73, 74) for forming the plurality of current paths; and an upper-stage switching element (Pch transistor 77) which is series-connected to an upper stage of each of the lower-stage switching elements, and forms a current path for determining a shunt value of the constant currents supplied to the plurality of current paths; and the decode means outputs such a control signal (upper-stage current path selection signal 78, low-stage current path selection signals 71, 72) capable of independently controlling the respective switching elements.
A D/A converter, according to a fourth aspect of the present invention, is featured by that in the D/A converter, a plurality of D/A converters (D/A converter 603) are connected in parallel to each other; and the D/A converter is comprised of decode means (decode circuit 601) for outputting such a signal (D/A converter control signal 602) used to control the respective decode means which constitute the D/A converters in response to a digital input signal (digital input signal 600), respectively.
A D/A converter, according to a fifth aspect of the present invention, is featured by that in the D/A converter, the switch circuit includes: a Pch transistor (Pch transistors 73, 74, 77) for constituting each of the switching elements; and a switch (SW1, SW2, SW3) for selecting a constant voltage (bias voltage 77, 80) by which the Pch transistor is operated in a saturation region and for applying the selected constant voltage to a gate of the Pch transistor when the switching element is selectively turned ON in response to the control signal.
A D/A converter, according to a sixth aspect of the present invention, is featured by that in the D/A converter, the current-to-voltage converting means (current/voltage converting circuit 507, 508) maintains a potential at the output terminal of the switch circuit at a constant value by keeping a potential at the input terminal (current input terminal 90) of the current-to-voltage converting means constant (reference voltage VREF).
A D/A converter, according to a seventh aspect of the present invention, is featured by that in the D/A converter, the decode means selects the switch circuit in response to the digital input signal, and also outputs such a control signal used to supply a unit current to the switch circuit, the unit current being produced by shunting the constant current in correspondence with a total number of the selected switch circuits.
In this invention, the constant current is supplied to the switch circuits, and the constant current is equally distributed to a plurality of current paths of the switch circuits in response to the digital input signal, so that the output current value can be varied. As a result, in the prior art, the current value is increased/decreased in the unit of the constant current, whereas the current value can be increased/decreased based upon such a unit current produced by equally dividing the constant current, and also the resolution can be improved without increasing a total number of the constant current sources. While the resolution may be determined based upon a total number of these current paths, in the case that the constant current is divided into two current paths, the resulting resolution can be increased by 1 bit (namely, two times). Accordingly, when the same resolution as that of the conventional D/A converter is obtained, the necessary occupied area of the D/A converter according to the present invention may be reduced by xc2xd, or less. In other words, when the same occupied area is used, the resultant resolution may be increased more than two times higher than that of the prior art.
In this invention, the constant current of a single constant current source is shunted in correspondence with a total number of the switch circuits which are selected by operating the upper-stage switching elements. Furthermore, the shunted current is subdivided based upon a total number of such current paths which are formed by operating the lower-stage switching elements so as to obtain the unit current. As a consequence, the resolution can be improved without increasing a total number of these constant current sources. In addition, while a total number of the selected switch circuits is changed in response to the digital input signal, the current is variable in response to the quantity of these switch circuits, which is supplied to the current paths which form the unit current. As a result, the resolution in the vicinity of the center can be increased, as compared with that of the conventional structure. Also, since the unit current can be varied, the resolution can be readily changed, whereas the resolution of the conventional D/A converter is changed by controlling the capacity of the constant current source.
In this invention, the current can be equally divided into the respective current paths irrespective of the characteristics of the respective switching elements (transistors).
In this invention, since the potential at the input terminal of the current-to-voltage converting means is kept constant, the potential at the output terminal of the switch circuit can also be kept constant, which is connected to the input terminal. As a consequence, the current which flows through the current paths of the switch circuits can be equally divided in high precision.
In this invention, in particular, such a decode means can be obtained which may allocate the digital input signal to the analog output in such a manner that the quantizing noise in the vicinity of the center can become minimum in response to such an output signal as a sine wave having a large changing ratio in the vicinity of a center of this sine wave.